xsnegqp

VSX Scalar Negate Quad-Precision

xsnegqp vD, vB

Negates a 128-bit Quad float.

Details

Negates the sign bit of a 128-bit quad-precision floating-point value in VSR vB and stores the result in VSR vD. This is a simple bit-flip operation that does not affect FPSCR exception flags or condition registers.

Pseudocode Operation

vD ← vB with sign bit flipped

Programming Note

This instruction is used to negate a quad-precision floating-point value. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bit in the MSR register. The operation affects two consecutive doublewords, so ensure proper alignment of the source register.

Example

xsnegqp vd, vb

Encoding

Binary Layout
63
0
vD
6
0
11
vB
16
804
21
/
31
 
Format X-form
Opcode 0xFC100648
Extension VSX
Registers Altered MSR

Operands

  • vD
    Target
  • vB
    Source