vadduwm

Vector Add Unsigned Word Modulo

vadduwm vD, vA, vB

Adds 4 words modulo 2^32.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

128

21:31

 

Format VX-form

Opcode 0x10000080

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

vadduwm vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Adds each of four unsigned 32-bit words in vA to the corresponding word in vB, with results modulo 2^32 (wrapping on overflow). No status flags are affected; this is a basic VMX/AltiVec arithmetic operation.

Operation

for i in 0 to 3 do
  vD[i*32:(i+1)*32-1] ← (vA[i*32:(i+1)*32-1] + vB[i*32:(i+1)*32-1]) mod 2^32

Programming Note

This instruction is commonly used for performing element-wise addition of unsigned 32-bit integers in vector registers. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to avoid a Vector_Unavailable exception. The operation wraps around using modulo arithmetic, so there's no need to handle overflow separately. This instruction operates at the user privilege level and does not generate exceptions for normal arithmetic operations.