vadduwm

Vector Add Unsigned Word Modulo

vadduwm vD, vA, vB

Adds 4 words modulo 2^32.

Details

The vadduwm instruction performs an unsigned word addition modulo operation on the elements of two vector registers, VRA and VRB, and stores the results in the vector register VRT. Each element is treated as a 32-bit unsigned integer, and the low-order 32 bits of the sum are placed into the corresponding element of VRT.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 7
   src1 ←EXTZ(VSR[VRA+32].word[i])
   src2 ←EXTZ(VSR[VRB+32].word[i])
   VSR[VRT+32].word[i] ←CHOP32(src1 + src2)
end

Programming Note

This instruction is commonly used for performing element-wise addition of unsigned 32-bit integers in vector registers. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to avoid a Vector_Unavailable exception. The operation wraps around using modulo arithmetic, so there's no need to handle overflow separately. This instruction operates at the user privilege level and does not generate exceptions for normal arithmetic operations.

Example

vadduwm vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
128
21
 
Format VX-form
Opcode 0x10000080
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B