lxvll

Load VSX Vector with Length Left-justified X-form

lxvll XT,RA,RB

Loads a variable-length vector from memory into a VSX register, left-justifying the data.

Details

Loads a variable-length data element from memory into a VSX register, left-justifying the loaded bytes within the 128-bit register. The effective address is RA|0, and the length in bytes is taken from bits 0–6 of RB (capped at 16). Remaining bytes in the register are zeroed. No status fields are modified by this instruction.

Pseudocode Operation

EA ← (RA=0 ? 0 : GPR[RA])
len ← GPR[RB][0:6] & 0xF
for i ← 0 to (len - 1) do
  VSR[XT][i*8:(i*8)+7] ← MEM(EA + i, 1)
for i ← len to 15 do
  VSR[XT][i*8:(i*8)+7] ← 0

Programming Note

lxvll always performs storage accesses using Big-Endian byte-ordering. As such, care must be taken when using these instructions in Little-Endian systems.

Example

lxvll vs1, r4, r5

Encoding

Binary Layout
0
0
T
6
RA
11
RB
16
TX
30
 
Format X-form
Opcode 0x7C00025A
Extension VSX
Registers Altered MSR

Operands

  • XT
    Target VSX Register
  • RA
    Source General Purpose Register (Effective Address)
  • RB
    Source General Purpose Register (Length and Data)