lxvll

Load VSX Vector with Length Left-justified X-form

lxvll XT,RA,RB

Loads a variable-length vector from memory into a VSX register, left-justifying the data.

Encoding

Binary Layout

0

0:5

T

6:10

RA

11:15

RB

16:29

TX

30:31

 

Format X-form

Opcode 0x7C00025A

Extension VSX

Operands

• XT
  Target VSX Register
• RA
  Source General Purpose Register (Effective Address)
• RB
  Source General Purpose Register (Length and Data)

Example

lxvll vs1, r4, r5

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a variable-length data element from memory into a VSX register, left-justifying the loaded bytes within the 128-bit register. The effective address is RA|0, and the length in bytes is taken from bits 0-6 of RB (capped at 16). Remaining bytes in the register are zeroed. No status fields are modified by this instruction.

Operation

EA ← (RA=0 ? 0 : GPR[RA])
len ← GPR[RB][0:6] & 0xF
for i ← 0 to (len - 1) do
  VSR[XT][i*8:(i*8)+7] ← MEM(EA + i, 1)
for i ← len to 15 do
  VSR[XT][i*8:(i*8)+7] ← 0

Programming Note

lxvll always performs storage accesses using Big-Endian byte-ordering. As such, care must be taken when using these instructions in Little-Endian systems.