lxvll

Load VSX Vector with Length Left-justified X-form

lxvll XT,RA,RB

Loads a variable-length vector from memory into a VSX register, left-justifying the data.

Details

The lxvll instruction loads a variable-length vector from memory into a VSX register, left-justifying the data. The length of the data to be loaded is specified in bits 0:7 of GPR[RB].

Pseudocode Operation

if TX=0 & MSR.VSX=0 then VSX_Unavailable()
if TX=1 & MSR.VEC=0 then Vector_Unavailable()
EA ←(RA=0) ? 0 : GPR[RA]
nb ←EXTZ(GPR[RB].bit[0:7])
if nb > 16 then nb ←16
if nb > 0 then do i = 0 to nb-1
    VSR[32×TX+T].byte[i] ←MEM(EA+i,1)
end
if nb < 16 then do i = nb to 15
    VSR[32×TX+T].byte[i] ←0x00
end

Programming Note

lxvll always performs storage accesses using Big-Endian byte-ordering. As such, care must be taken when using these instructions in Little-Endian systems.

Example

lxvll vs1, r4, r5

Encoding

Binary Layout
0
0
T
6
RA
11
RB
16
TX
30
 
Format X-form
Opcode 0x7C00025A
Extension VSX
Registers Altered MSR

Operands

  • XT
    Target VSX Register
  • RA
    Source General Purpose Register (Effective Address)
  • RB
    Source General Purpose Register (Length and Data)