stdci

Store Doubleword Caching Inhibited

stdci RS, RA, RB

Stores a doubleword bypassing the cache.

Details

The Store Doubleword Caching Inhibited instruction stores a doubleword bypassing the cache.

Pseudocode Operation

Memory[address] <- r3

Example

stdci r3, r4, r5

Encoding

Binary Layout
31
0
RS
6
RA
11
RB
16
1015
21
/
31
 
Format X-form
Opcode 0x7C0007EF
Extension Base

Operands

  • RS
    Source
  • RA
    Base
  • RB
    Index