lxvrhx

Load VSX Vector Rightmost Halfword Indexed

lxvrhx XT,RA,RB

Loads a halfword from memory into the rightmost element of a VSX vector register.

Encoding

Binary Layout

0

0:5

T

6:10

RA

11:15

RB

16:20

TX

21:31

 

Format X-form

Opcode 0x7C00005A

Extension VSX

Operands

• XT
  Target Vector-Scalar Register
• RA
  Source General Purpose Register (Base Address)
• RB
  Source General Purpose Register (Index)

Example

lxvrhx vs1, r4, r5

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a 16-bit halfword from memory and places it in the rightmost (least significant) halfword position of a VSX register, with all other bits set to 0. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.

Operation

EA ← (RA=0 ? 0 : GPR[RA]) + GPR[RB]
VSR[XT] ← (0x000000000000000000000000 || MEM(EA, 2))

Programming Note

The lxvrhx instruction is used to load a halfword from memory into the rightmost element of a VSX vector register. Ensure that the VSX facility is enabled in the MSR register; otherwise, an exception will be raised. The address calculation uses two general-purpose registers, RA and RB, where RA can be zero. The loaded halfword is placed in the rightmost halfword element (element 7) of the specified VSX vector register, with all other elements set to zero. Endianness affects how the halfword is stored in the vector register; ensure proper handling for both big-endian and little-endian systems.