lxvrhx

Load VSX Vector Rightmost Halfword Indexed

lxvrhx XT,RA,RB

Loads a halfword from memory into the rightmost element of a VSX vector register.

Details

The lxvrhx instruction loads a halfword from memory into the rightmost element of a VSX vector register. The address is calculated by adding the contents of two general-purpose registers, RA and RB. If RA is zero, it is treated as zero. The loaded halfword is placed in the rightmost halfword element (element 7) of the VSX vector register specified by XT, with all other elements set to zero.

Pseudocode Operation

if MSR.VSX=0 then
    VSX_Unavailable()
EA = ((RA=0) ? 0 : GPR[RA]) + GPR[RB]
VSR[32×TX+T] = EXTZ128(MEM(EA,2))
load_data = MEM(EA,2)
if Big-Endian then
    VSR[XT].hword[7] = load_data
else if Little-Endian then
    VSR[XT].hword[7] = REVERSE(load_data)
for i from 0 to 6 do
    VSR[XT].hword[i] = 0

Programming Note

The lxvrhx instruction is used to load a halfword from memory into the rightmost element of a VSX vector register. Ensure that the VSX facility is enabled in the MSR register; otherwise, an exception will be raised. The address calculation uses two general-purpose registers, RA and RB, where RA can be zero. The loaded halfword is placed in the rightmost halfword element (element 7) of the specified VSX vector register, with all other elements set to zero. Endianness affects how the halfword is stored in the vector register; ensure proper handling for both big-endian and little-endian systems.

Example

lxvrhx vs1, r4, r5

Encoding

Binary Layout
0
0
T
6
RA
11
RB
16
TX
21
 
Format X-form
Opcode 0x7C00005A
Extension VSX
Registers Altered MSR

Operands

  • XT
    Target Vector-Scalar Register
  • RA
    Source General Purpose Register (Base Address)
  • RB
    Source General Purpose Register (Index)