vcfsx

Vector Convert from Signed Fixed-Point Word to Single-Precision Floating-Point

vcfsx vD, vB, UIM

Converts signed fixed-point values in a vector register to single-precision floating-point values.

Encoding

Binary Layout
4
0:5
vD
6:10
UIM
11:15
vB
16:20
842
21:31
 
Format VX-form
Opcode 0x1000034A
Extension VMX (AltiVec)

Operands

  • vD
    Target
  • vB
    Source
  • UIM
    Fraction bits
  • VRT
    Target Vector Register
  • VRB
    Source Vector Register

Example

vcfsx vd, vb, uim

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vcfsx, each word element of the source vector register VRB is converted to a nearest single-precision floating-point value and divided by 2^UIM. The results are stored in the corresponding word elements of the target vector register VRT.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src ← VSR[VRB+32].word[i]
    VSR[VRT+32].word[i] ← bfp32_CONVERT_FROM_SI32(src, UIM)
end

Extended Mnemonics

Extended Mnemonic Equivalent Instruction
vcsxwfp

Programming Note

The fixed-point integers used by the Vector Convert instructions can be interpreted as consisting of 32-UIM integer bits followed by UIM fraction bits.