xscmpexpqp

VSX Scalar Compare Exponents Quad-Precision

xscmpexpqp BF, vA, vB

Compares the exponents of two quad-precision floating-point values and updates the condition register.

Encoding

Binary Layout

0:5

6:8

9:10

11:15

16:20

228

21:30

Format X-form

Opcode 0xFC000148

Extension VSX

Operands

BF
CR Field
vA
Src A
vB
Src B
VRA
Vector Register A
VRB
Vector Register B

Example

xscmpexpqp cr0, va, vb

Registers Altered

CR, FPSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The exponent of src1 is compared with the exponent of src2 as unsigned integer values. The result of the compare is placed into FPCC and CR field BF.

Operation

if MSR.VSX=0 then VSX_Unavailable()

reset_flags()

src1 ← VSR[VRA+32]
src2 ← VSR[VRB+32]

src1.exponent ← EXTZ(src1.bit[1:15])
src2.exponent ← EXTZ(src2.bit[1:15])
src1.fraction ← EXTZ(src1.bit[16:127])
src2.fraction ← EXTZ(src2.bit[16:127])

src1.class.NaN ← (src1.exponent = 32767) & (src1.fraction != 0)
src2.class.NaN ← (src2.exponent = 32767) & (src2.fraction != 0)

lt_flag ← (src1.exponent < src2.exponent)
gt_flag ← (src1.exponent > src2.exponent)
eq_flag ← (src1.exponent = src2.exponent)
uo_flag ← src1.class.NaN | src2.class.NaN

CR.bit[4×BF+32] ← FPSCR.FL ← !uo_flag & lt_flag
CR.bit[4×BF+33] ← FPSCR.FG ← !uo_flag & gt_flag
CR.bit[4×BF+34] ← FPSCR.FE ← !uo_flag & eq_flag
CR.bit[4×BF+35] ← FPSCR.FU ← uo_flag

Programming Note

This instruction compares the exponents of two quad-precision floating-point numbers. Ensure that VSX is enabled in the MSR register to avoid exceptions. The result is stored in both the CR and FPSCR registers, with flags indicating less than, greater than, equal, or unordered comparisons. Handle NaN values appropriately as they set the unordered flag.