xststdcdp

VSX Scalar Test Data Class Double-Precision

xststdcdp BF, XB, DCM

Tests the data class of a double-precision floating-point value in VSR[XB] and sets bits in CR field BF and FPCC accordingly.

Details

The instruction tests the data class of the double-precision floating-point value in VSR[XB].dword[0] and sets bits in CR field BF and FPCC based on the result.

Pseudocode Operation

if MSR.VSX=0 then
    VSX_Unavailable()
src ← VSR[32×BX+B].dword[0]
exponent ← src.bit[1:11]
fraction ← src.bit[12:63]
class.NaN ← (exponent = 0x7FF) & (fraction != 0)
class.Infinity ← (exponent = 0x7FF) & (fraction = 0)
class.Zero ← (exponent = 0x000) & (fraction = 0)
class.Denormal ← (exponent = 0x000) & (fraction != 0)
match ←
    (DCMX.bit[0] & class.NaN) |
    (DCMX.bit[2] & class.Infinity & sign) |
    (DCMX.bit[3] & class.Zero & !sign) |
    (DCMX.bit[4] & class.Zero & sign) |
    (DCMX.bit[5] & class.Denormal & !sign) |
    (DCMX.bit[6] & class.Denormal & sign)
CR.bit[4×BF+32] ← FPSCR.FL ← src.sign
CR.bit[4×BF+33] ← FPSCR.FG ← 0b0
CR.bit[4×BF+34] ← FPSCR.FE ← match
CR.bit[4×BF+35] ← FPSCR.FU ← 0b0

Programming Note

This instruction is used to test the data class of a double-precision floating-point value. Ensure that VSX (Vector Scalar Extensions) is enabled in the MSR register, otherwise, an exception will be raised. The result updates both the CR and FPSCR registers, so check these for further processing. Be cautious with alignment; the source vector register must be properly aligned to avoid undefined behavior.

Example

xststdcdp cr0, vs3, 0

Encoding

Binary Layout
60
0
BF
6
/
9
DCM
16
XB
362
 
Format XX2-form
Opcode 0xF000016A
Extension VSX
Registers Altered CR, FPSCR

Operands

  • BF
    CR Field
  • XB
    Source
  • DCM
    Data Class Mask
  • DCMX
    Data Class Mask