stxvll

Store VSX Vector with Length Left-justified

stxvll XS,RA,RB

Stores a left-justified vector from a VSX register to memory.

Details

The stxvll instruction stores the contents of a VSX register into memory, starting at the effective address specified by RA. The number of bytes stored is determined by the lower 8 bits of RB. If the number of bytes exceeds 16, it is capped at 16.

Pseudocode Operation

if SX=0 & MSR.VSX=0 then VSX_Unavailable()
if SX=1 & MSR.VEC=0 then Vector_Unavailable()
EA ←(RA=0) ? 0 : GPR[RA]
nb ←EXTZ(GPR[RB].bit[0:7])
if nb>16 then nb ←16
if nb>0 then do i = 0 to nb-1
    MEM(EA+i,1) ←VSR[32×SX+S].byte[i]
end

Programming Note

stxvll always performs storage accesses using Big-Endian byte-ordering. As such, care must be taken when using these instructions in Little-Endian systems.

Example

stxvll vs1, r4, r5

Encoding

Binary Layout
0
0
S
1
RA
6
RB
11
SX
16
 
Format X-form
Opcode 0x7C00035A
Extension VSX
Registers Altered MSR

Operands

  • XS
    VSX Register
  • RA
    Source General Purpose Register (Effective Address)
  • RB
    General Purpose Register containing the number of bytes to store