stxvll

Store VSX Vector with Length Left-justified

stxvll XS,RA,RB

Stores a left-justified vector from a VSX register to memory.

Encoding

Binary Layout

0

S

RA

RB

SX

 

Format X-form

Opcode 0x7C00035A

Extension VSX

Operands

• XS
  VSX Register
• RA
  Source General Purpose Register (Effective Address)
• RB
  General Purpose Register containing the number of bytes to store

Example

stxvll vs1, r4, r5

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Stores a variable-length left-justified portion of a VSX vector to memory. The number of bytes to store (0-16) is specified in the low-order 4 bits of RB; bytes are stored starting at the effective address (RA|0). This VSX instruction does not affect condition registers or status flags.

Operation

EA ← (RA|0)
length ← RB[60:63]
for i ← 0 to length-1 do
  [EA+i] ← VSR[XS][8*i:8*i+7]
end for

Programming Note

stxvll always performs storage accesses using Big-Endian byte-ordering. As such, care must be taken when using these instructions in Little-Endian systems.