stax

Store Atomic

stax RS,RA,RB

Performs an atomic update to an aligned memory location based on the function code (FC) specified.

Details

The stax instruction performs an atomic operation on a memory location. The specific operation is determined by the function code (FC). The operands include a general-purpose register (RS), a base address register (RA), and an offset (RB).

Pseudocode Operation

EA <- (RA) + (RB)
switch (FC) {
case 0x00:
    t <- mem(EA, s)
    t2 <- t + (RS)
    mem(EA,s) <- t2
    break;
case 0x01:
    t <- mem(EA, s)
    t2 <- t ⊕ (RS)
    mem(EA,s) <- t2
    break;
case 0x02:
    t <- mem(EA, s)
    t2 <- t | (RS)
    mem(EA,s) <- t2
    break;
case 0x03:
    t <- mem(EA, s)
    t2 <- t & (RS)
    mem(EA,s) <- t2
    break;
case 0x04:
    t <- mem(EA, s)
    if (RS) >u t then
        mem(EA,s) <- (RS)
    break;
case 0x05:
    t <- mem(EA, s)
    if (RS) > t then
        mem(EA,s) <- (RS)
    break;
case 0x06:
    t <- mem(EA, s)
    if (RS) <u t then
        mem(EA,s) <- (RS)
    break;
case 0x07:
    t <- mem(EA, s)
    if (RS) < t then
        mem(EA,s) <- (RS)
    break;
case 0x18:
    t <- mem(EA, s)
    t2 <- mem(EA+s, s)
    if t = t2 then
        mem(EA,s) <- (RS)
        mem(EA+s,s) <- (RS)
    break;
default:
    reserved
}

Programming Note

For word atomics, only the least significant word of each source register is used.

Example

stax r3, r4, r5

Encoding

Binary Layout

Format X-form

Opcode

Extension Base

Operands

RS
Source General Purpose Register
RA
Base Address General Purpose Register
RB
Offset General Purpose Register