xvbf16ger2

VSX Vector BFloat16 GER (Rank-2 Update)

xvbf16ger2 AT, XA, XB

Performs BFloat16 (Brain Float) matrix multiply accumulate.

Encoding

Binary Layout

60

0:5

AT

6:10

XA

11:15

XB

16:20

51

21:31

 

Format XX3-form

Opcode 0xEC000198

Extension MMA

Operands

• AT
  Accumulator
• XA
  Src A (BF16)
• XB
  Src B (BF16)

Example

xvbf16ger2 acc0, vs2, vs3

Registers Altered

ACC

Related

More in MMA

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a rank-2 outer product of two BFloat16 (Brain Float) vectors, accumulating results into the 512-bit accumulator AT. BFloat16 is a truncated 32-bit floating-point format used in machine-learning workloads. This MMA instruction does not affect condition registers or status fields.

Operation

for i = 0 to 31 do
  for j = 0 to 31 do
    ACC[AT][result_lane] ← ACC[AT][result_lane] + (bf16)XA[16×i:16×i+15] × (bf16)XB[16×j:16×j+15]
  end for
end for

Programming Note

The xvbf16ger2 instruction is used for performing a rank-2 update on the accumulator using bfloat16 values from two VSX registers. Ensure that the input registers are properly aligned and that the operation does not exceed the bounds of the accumulator to avoid saturation issues. This instruction operates at privilege level 0.