xvi8ger4

VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)

xvi8ger4 AT, XA, XB

Performs an 8-bit integer outer product (GER) and accumulates into a 512-bit register.

Details

The xvi8ger4 instruction performs a rank-4 update on VSX vector elements, multiplying and accumulating the results based on specified masks.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

PMSK ←0b1111
XMSK ←0b1111
YMSK ←0b1111

do i = 0 to 3
do j = 0 to 3
   if XMSK.bit[i] & YMSK.bit[j] then do
      prod0 ←(PMSK.bit[0]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].byte[0]) * EXTZ(VSR[32×BX+B].word[j].byte[0])
      prod1 ←(PMSK.bit[1]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].byte[1]) * EXTZ(VSR[32×BX+B].word[j].byte[1])
      prod2 ←(PMSK.bit[2]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].byte[2]) * EXTZ(VSR[32×BX+B].word[j].byte[2])
      prod3 ←(PMSK.bit[3]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].byte[3]) * EXTZ(VSR[32×BX+B].word[j].byte[3])

      psum ←prod0 + prod1 + prod2 + prod3

      ACC[AT][i].word[j] ←CHOP32( psum )
   end
   else
      ACC[AT][i][j] ←0x0000_0000
end
end

Programming Note

The xvi8ger4 instruction requires the VSX facility to be enabled in the MSR register. It performs a rank-4 update on VSX vector elements, multiplying and accumulating 8-bit signed/unsigned integers based on specified masks. Ensure that the VSX feature is available and properly configured before using this instruction.

Example

xvi8ger4 acc0, vs2, vs3

Encoding

Binary Layout
0
0
AT
6
XA
10
XB
14
3
18
AXBX
21
 
Format XX3-form
Opcode 0xF0000022
Extension MMA
Registers Altered MSR

Operands

  • AT
    Accumulator
  • XA
    Vector A (8-bit)
  • XB
    Vector B (8-bit)