xvi8ger4

VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)

xvi8ger4 AT, XA, XB

Performs an 8-bit integer outer product (GER) and accumulates into a 512-bit register.

Details

Performs a rank-4 outer product of two 8-bit signed/unsigned integer vectors, accumulating the result into the 512-bit accumulator AT. The operation treats elements of XA and XB as 8-bit integers, computes pairwise products, and accumulates them into 32-bit or 64-bit result lanes within the accumulator. This MMA instruction does not affect condition registers or status fields.

Pseudocode Operation

for i = 0 to 15 do
  for j = 0 to 15 do
    ACC[AT][4×(i×16+j)] ← ACC[AT][4×(i×16+j)] + (int8)XA[8×i:8×i+7] × (int8)XB[8×j:8×j+7]
  end for
end for

Programming Note

The xvi8ger4 instruction requires the VSX facility to be enabled in the MSR register. It performs a rank-4 update on VSX vector elements, multiplying and accumulating 8-bit signed/unsigned integers based on specified masks. Ensure that the VSX feature is available and properly configured before using this instruction.

Example

xvi8ger4 acc0, vs2, vs3

Encoding

Binary Layout
0
0
AT
6
XA
10
XB
14
3
18
AXBX
21
 
Format XX3-form
Opcode 0xF0000022
Extension MMA
Registers Altered MSR

Operands

  • AT
    Accumulator
  • XA
    Vector A (8-bit)
  • XB
    Vector B (8-bit)