vsubcuq

Vector Subtract Carryout Unsigned Quadword

vsubcuq vD, vA, vB

Subtracts the contents of two vector registers, adds one, and writes the carry-out to another register.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

1344

21:31

Format VX-form

Opcode 0x10000540

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vsubcuq vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vsubcuq, the difference between the contents of VSR[VRA+32] and the one's complement of VSR[VRB+32], plus one, is placed into VSR[VRT+32]. The carry out is also written to VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
src1 ←EXTZ(VSR[VRA+32])
src2 ←EXTZ(¬VSR[VRB+32])
VSR[VRT+32] ←CHOP128((src1 + src2 + 1) >> 128)

Programming Note

The Vector Subtract Unsigned Quadword instructions support efficient wide-integer subtraction.