vstrihr.

Vector String Isolate Halfword Right-justified (Record)

vstrihr. VRT,VRB

Isolates the rightmost non-zero halfword in a vector string.

Encoding

Binary Layout

0:5

VRT

6:10

VRB

11:15

16:20

21:31

Format VC-form

Opcode 0x1003000D

Extension VMX (AltiVec)

Operands

VRT
Target Vector Register
VRB
Source Vector Register

Example

vstrihr v1, v3

Registers Altered

CR6 (if Rc=1)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

From right to left, the contents of each halfword element of VSR[VRB+32] are placed into the corresponding halfword element in VSR[VRT+32]. If a halfword element in VSR[VRB+32] is found to contain 0, the corresponding halfword element and all halfword elements to the left of that halfword element in VSR[VRT+32] are set to 0.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
null_found ← 0
while (!null_found) do i = 0 to 7
    null_found ← (VSR[VRB+32].hword[7-i] = 0)
    VSR[VRT+32].hword[7-i] ← VSR[VRB+32].hword[7-i]
end
do j = i to 7
    VSR[VRT+32].hword[7-j] ← 0
end
if Rc=1 then
    CR.field[6] ← 0b00 || null_found || 0b0

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.