vsububm

Vector Subtract Unsigned Byte Modulo

vsububm vD, vA, vB

Subtracts the contents of two vector registers and updates the result in another vector register using modulo operation for bytes.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1024

21:31

Format VX-form

Opcode 0x10000400

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vsububm vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vsububm, each byte element in VSR[VRB+32] is subtracted from the corresponding byte element in VSR[VRA+32], and the result is placed into the corresponding byte element of VSR[VRT+32]. The operation uses modulo arithmetic.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ←EXTZ(VSR[VRA+32].byte[i])
    src2 ←EXTZ(VSR[VRB+32].byte[i])
    VSR[VRT+32].byte[i] ←CHOP8(src1 + ¬src2 + 1)
end

Programming Note

This instruction performs vectorized byte-wise subtraction with modulo arithmetic. Ensure that the Vector Facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious of potential overflow issues due to the modulo operation, which can wrap around values. This instruction operates at a privilege level where the Vector Facility is accessible.