vsububm

Vector Subtract Unsigned Byte Modulo

vsububm vD, vA, vB

Subtracts the contents of two vector registers and updates the result in another vector register using modulo operation for bytes.

Details

For vsububm, each byte element in VSR[VRB+32] is subtracted from the corresponding byte element in VSR[VRA+32], and the result is placed into the corresponding byte element of VSR[VRT+32]. The operation uses modulo arithmetic.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ←EXTZ(VSR[VRA+32].byte[i])
    src2 ←EXTZ(VSR[VRB+32].byte[i])
    VSR[VRT+32].byte[i] ←CHOP8(src1 + ¬src2 + 1)
end

Programming Note

This instruction performs vectorized byte-wise subtraction with modulo arithmetic. Ensure that the Vector Facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious of potential overflow issues due to the modulo operation, which can wrap around values. This instruction operates at a privilege level where the Vector Facility is accessible.

Example

vsububm vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1024
 
Format VX-form
Opcode 0x10000400
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register