mtvsrdd

Move To VSR Double Double

mtvsrdd XT, RA, RB

Moves the contents of two general-purpose registers into a vector-scalar register (VSR) as doublewords.

Encoding

Binary Layout

31

0:5

XT

6:10

RA

11:15

RB

16:20

435

21:30

/

31

 

Format X-form

Opcode 0x7C000366

Extension VSX

Operands

• XT
  Target VSR
• RA
  High GPR
• RB
  Low GPR

Example

mtvsrdd vs1, r4, r5

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Moves the contents of two general-purpose registers into a VSR as doublewords, with RA forming the high doubleword and RB forming the low doubleword. This is a VSX instruction that does not affect condition registers or status fields.

Operation

XT[0:63] ← RA
XT[64:127] ← RB

Programming Note

For TX=0, mtvsrdd is treated as a VSX instruction in terms of resource availability. For TX=1, mtvsrdd is treated as a Vector instruction in terms of resource availability.