stxvl

Store VSX Vector Length

stxvl XS, RA, RB

Stores a specified number of bytes from a VSX vector register to memory.

Details

The stxvl instruction stores a specified number of bytes from the VSX vector register VSR[XS] to memory. The number of bytes to store is determined by the lower 8 bits of GPR[RB]. If the number of bytes is less than 16, only those bytes are stored; otherwise, the entire quadword (16 bytes) is stored. The byte order depends on the endianness setting.

Pseudocode Operation

if SX=0 & MSR.VSX=0 then VSX_Unavailable()
if SX=1 & MSR.VEC=0 then Vector_Unavailable()
EA ←(RA=0) ? 0 : GPR[RA]
nb ←EXTZ(GPR[RB].bit[0:7])
if nb>16 then nb ←16
if MSR.LE = 0 then       // Big-Endian byte-ordering
    store_data ←VSR[32×SX+S].byte[0:nb-1]
else                     // Little-Endian byte ordering
    store_data ←VSR[32×SX+S].byte[16-nb:15]
MEM(EA,nb) ←store_data

Programming Note

Storing N bytes of data from the source VSR using stxvl in BE mode, results in the leftmost N bytes in the source VSR being placed in storage, starting with the leftmost byte of the source VSR. Storing N bytes of data from the source VSR using stxvl in LE mode, results in the rightmost N bytes in the source VSR being placed in storage, starting with the rightmost byte of the source VSR.

Example

stxvl vs1, r4, r5

Encoding

Binary Layout
31
0
XS
1
RA
6
RB
11
397
16
 
Format XX1-form
Opcode 0x7C00031D
Extension VSX
Registers Altered MSR

Operands

  • XS
    Source
  • RA
    Base
  • RB
    Length Reg