vmsumcud

Vector Multiply-Sum & write Carry-out Unsigned Doubleword

vmsumcud VRT,VRA,VRB,VRC

Performs vector multiply-sum and writes the carry-out of the low-order 128 bits to a destination register.

Details

The instruction performs two unsigned doubleword multiplications, sums the results along with an additional source register, and writes the carry-out of the low-order 128 bits to the destination register.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()

temp ←EXTZ(VSR[VRC+32])
do i = 0 to 1
    src1  ←EXTZ(VSR[VRA+32].dword[i])
    src2  ←EXTZ(VSR[VRB+32].dword[i])
    temp ←temp + (src1 × src2)
end

VSR[VRT+32] ←CHOP128(temp >> 128)

Programming Note

This instruction is useful for performing high-precision arithmetic operations involving unsigned doublewords. Ensure that the vector facility is enabled by checking and setting the appropriate bits in the Machine State Register (MSR). Be cautious of overflow conditions, as the carry-out from the low-order 128 bits is written to the destination register. The instruction operates on 64-bit elements, so ensure proper alignment for optimal performance.

Example

vmsumcud v1, v2, v3, v4

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
VRC
21
23
26
 
Format VA-form
Opcode 0x7C000000
Extension VMX (AltiVec)

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register
  • VRC
    Source Vector Register