xscvqpsdz

VSX Scalar Convert with round to zero Quad-Precision to Signed Doubleword format X-form

xscvqpsdz VRT,VRB

Converts a quad-precision floating-point value to a signed doubleword integer, rounding towards zero.

Encoding

Binary Layout

0

0:5

VRT

6:10

VRB

11:20

11000000000000000000000000000000

21:31

 

Format X-form

Opcode 0xFC190688

Extension VSX

Operands

• VRT
  Target Vector Register
• VRB
  Source Vector Register

Example

xscvqpsdz v1, v3

Registers Altered

FPSCR.FPRF, FPSCR.FR, FPSCR.FI, FPSCR.VXSNAN, FPSCR.VXCVI, FPSCR.XX

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Converts a quad-precision floating-point value from the source VSR to a signed 64-bit doubleword integer using round-toward-zero mode and stores the result in the target VSR. Only the scalar element is processed. Invalid conversions saturate to the appropriate signed limit; FPSCR status is updated.

Operation

VRT[0:63] ← ConvertToSignedDoubleword_RoundTowardZero(VRB[0:127])
VRT[64:127] ← 0

Programming Note

The xscvqpsdz instruction is used to convert a quad-precision floating-point value to a signed doubleword integer, rounding towards zero. Ensure that the VSX facility is enabled (MSR.VSX=1) before using this instruction; otherwise, it will raise an exception. Be cautious of NaN and infinity values, as they result in specific outputs and set flags indicating exceptions. The instruction handles overflow by saturating to the maximum or minimum signed doubleword value.