xscvqpsdz

VSX Scalar Convert with round to zero Quad-Precision to Signed Doubleword format X-form

xscvqpsdz VRT,VRB

Converts a quad-precision floating-point value to a signed doubleword integer, rounding towards zero.

Details

The xscvqpsdz instruction converts the contents of VSR[VRB+32] from a quad-precision floating-point value to a signed doubleword integer, rounding towards zero. The result is placed into doubleword element 0 of VSR[VRT+32]. Doubleword element 1 of VSR[VRT+32] is set to 0.

Pseudocode Operation

if MSR.VSX=0 then
    VSX_Unavailable()
reset_xflags()
src ←bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
vxsnan_flag ←0
vxcvi_flag ←0
if src.class.QNaN | src.class.SNaN then do
    result ←0x8000_0000_0000_0000
    vxsnan_flag ←src.class.SNaN
    vxcvi_flag ←1
end else if src.class.Infinity then do
    vxcvi_flag ←1
    if src.sign = 0 then
        result ←0x7FFF_FFFF_FFFF_FFFF
    else
        result ←0x8000_0000_0000_0000
    end
end else if src.class.Zero then
    result ←0x0000_0000_0000_0000
else do
    rnd ←bfp_ROUND_TO_INTEGER(0b001,src)
    if bfp_COMPARE_GT(rnd, +263-1) then do
        result ←0x7FFF_FFFF_FFFF_FFFF
        vxcvi_flag ←1
    end else if bfp_COMPARE_LT(rnd, -263) then do
        result ←0x8000_0000_0000_0000
        vxcvi_flag ←1
    end else do
        result ←si64_CONVERT_FROM_BFP(rnd)
        if xx_flag=1 then SetFX(FPSCR.XX)
    end
end
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxcvi_flag=1  then SetFX(FPSCR.VXCVI)
vx_flag ←vxsnan_flag | vxcvi_flag
ex_flag ←FPSCR.VE & vx_flag
if ex_flag=0 then do
    VSR[VRT+32].dword[0] ←result
    VSR[VRT+32].dword[1] ←0x0000_0000_0000_0000
end
FPSCR.FR ←(vx_flag=0) & inc_flag
FPSCR.FI ←(vx_flag=0) & xx_flag

Programming Note

The xscvqpsdz instruction is used to convert a quad-precision floating-point value to a signed doubleword integer, rounding towards zero. Ensure that the VSX facility is enabled (MSR.VSX=1) before using this instruction; otherwise, it will raise an exception. Be cautious of NaN and infinity values, as they result in specific outputs and set flags indicating exceptions. The instruction handles overflow by saturating to the maximum or minimum signed doubleword value.

Example

xscvqpsdz v1, v3

Encoding

Binary Layout

VRT

VRB

11000000000000000000000000000000

Format X-form

Opcode 0xFC190688

Extension VSX

Registers Altered FPSCR.FPRF, FPSCR.FR, FPSCR.FI, FPSCR.VXSNAN, FPSCR.VXCVI, FPSCR.XX

Operands

VRT
Target Vector Register
VRB
Source Vector Register