xsmsubasp

VSX Scalar Multiply Subtract Add Pair Single Precision

xsmsubasp XT,XA,XB

Performs a multiply-subtract-add operation on single-precision floating-point values.

Encoding

Binary Layout
60
0:5
XT
6:10
XA
11:15
XB
16:20
136
21:31
 
Format X-form
Opcode 0xF0000088
Extension VSX

Operands

  • XT
    Target Vector-Scalar Register
  • XA
    Source Vector-Scalar Register
  • XB
    Source Vector-Scalar Register
  • FRT
    Target Floating Point Register
  • FRB
    Source Floating Point Register
  • FRA
    Source Floating Point Register

Example

xsmsubasp vs1, vs2, vs3

Registers Altered

FPSCR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a fused multiply-subtract-add operation on scalar single-precision floating-point values. The operation computes (XA × XB) - XT + implicit_addend and stores the result in XT. This MMA/VSX fusion instruction updates FPSCR with exception flags and follows IEEE 754 rounding semantics.

Operation

XT ← (XA × XB) - XT + (addend)
FPSCR ← updated with exception flags and rounding

Programming Note

See Table 7.10, “VSX Scalar Floating-Point Final Result,” on page 618.