xvcvdpuxds

Vector Convert Double-Precision to Unsigned Doubleword with Round to Zero

xvcvdpuxds XT, XB

Converts double-precision floating-point values in a vector to unsigned doublewords using round towards zero.

Details

This instruction converts each element of the source vector (VSR[XB]) from double-precision floating-point format to an unsigned 64-bit integer, rounding towards zero. The result is stored in the corresponding element of the target vector (VSR[XT]). If any element results in a NaN or SNaN, VXSNAN and VXCVI are set accordingly.

Pseudocode Operation

for i = 0 to 1 do
    src <- VSR[XB][i]
    if src is a QNaN then
        T(Nmin), fx(VXCVI)
        if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode then error()
    else if src is a SNaN then
        T(Nmin), fx(VXCVI), fx(VXSNAN)
        if FPSCR.VXSNAN=0 and MSR.FE1!=ignore-exception-mode then error()
    else if src ≤ Nmin-1 then
        T(Nmin), fx(VXCVI)
        if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode then error()
    else if Nmin-1 < src < Nmin then
        if FPSCR.VE=0 then
            T(Nmin), fx(XX)
            if FPSCR.XX=0 and MSR.FE1!=ignore-exception-mode then error()
        else
            fx(XX), error()
    else if src = Nmin then
        T(Nmin)
    else if Nmin < src < Nmax then
        if FPSCR.VE=0 then
            T(f2i(trunc(src))), fx(XX)
            if FPSCR.XX=0 and MSR.FE1!=ignore-exception-mode then error()
        else
            fx(XX), error()
    else if src = Nmax then
        T(Nmax)
    else if Nmax < src < Nmax+1 then
        if FPSCR.VE=0 then
            T(Nmax), fx(XX)
            if FPSCR.XX=0 and MSR.FE1!=ignore-exception-mode then error()
        else
            fx(XX), error()
    else if src ≥ Nmax+1 then
        T(Nmin), fx(VXCVI)
        if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode then error()
    end if
end for

Programming Note

xvcvdpuxds rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Double-Precision Integer instruction that corresponds to the desired rounding mode.

Example

xvcvdpuxds vs1, vs3

Encoding

Binary Layout
60
0
XT
6
/
11
XB
16
456
21
BX
30
TX
31
 
Format XX2-form
Opcode 0xF00001C8
Extension VSX
Registers Altered FPSCR, VXSNAN, VXCVI, XX

Operands

  • XT
    Target
  • XB
    Source
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register