vmulosb

Vector Multiply Odd Signed Byte

vmulosb vD, vA, vB

Multiplies odd signed bytes to halfwords.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

264

21:31

Format VX-form

Opcode 0x10000108

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B

Example

vmulosb vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies the odd-indexed signed bytes from vA and vB, producing signed halfword results in vD. Operates on bytes at indices 1, 3, 5, 7, 9, 11, 13, 15, generating four halfword products. No condition flags are affected.

Operation

vD[0:15] ← (vA[8:15] × vB[8:15]) as signed
vD[16:31] ← (vA[24:31] × vB[24:31]) as signed
vD[32:47] ← (vA[40:47] × vB[40:47]) as signed
vD[48:63] ← (vA[56:63] × vB[56:63]) as signed
vD[64:79] ← (vA[72:79] × vB[72:79]) as signed
vD[80:95] ← (vA[88:95] × vB[88:95]) as signed
vD[96:111] ← (vA[104:111] × vB[104:111]) as signed
vD[112:127] ← (vA[120:127] × vB[120:127]) as signed

Programming Note

This instruction is useful for performing element-wise multiplication of odd-numbered bytes from two vectors, storing the results as signed halfwords. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation respects byte ordering, so developers must ensure proper alignment and data format to avoid unexpected results.