vmulosb

Vector Multiply Odd Signed Byte

vmulosb vD, vA, vB

Multiplies odd signed bytes to halfwords.

Details

The Vector Multiply Odd Signed Byte instruction multiplies each odd-numbered byte (1st, 3rd, 5th, and 7th bytes) of the elements in two vector registers VRA and VRB. The results are stored as signed halfwords in the corresponding positions of the destination vector register VRT.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 7
   src1 ←EXTS(VSR[VRA+32].byte[2×i+1])
   src2 ←EXTS(VSR[VRB+32].byte[2×i+1])

   VSR[VRT+32].hword[i] ←CHOP16(src1 × src2)
end

Programming Note

This instruction is useful for performing element-wise multiplication of odd-numbered bytes from two vectors, storing the results as signed halfwords. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation respects byte ordering, so developers must ensure proper alignment and data format to avoid unexpected results.

Example

vmulosb vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
264
21
 
Format VX-form
Opcode 0x10000108
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B