srawi

Shift Right Algebraic Word Immediate

srawi RA, RS, SH

Shifts the contents of a register right by an immediate value and replicates the sign bit.

Encoding

Binary Layout

31

0:5

RS

6:10

RA

11:15

SH

16:20

824

21:30

Rc

31

 

Format X-form

Opcode 0x7C000670

Extension Base

Operands

• RA
  Target Register
• RS
  Source Register
• SH
  Shift Amount (0-31)
• RT
  Target General Purpose Register

Example

srawi r3, r4, 5

// r3 = r4 >> 5 (Signed).

Registers Altered

CR0, XER

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The low-order 32 bits of register RS are shifted right SH bits. Bits shifted out of position 63 are lost. Bit 32 of RS is replicated to fill the vacated positions on the left. The 32-bit result is placed into RA32:63. Bit 32 of RS is replicated to fill RA0:31. CA and CA32 are set to 1 if the low-order 32 bits of (RS) contain a negative number and any 1-bits are shifted out of position 63; otherwise CA and CA32 are set to 0. A shift amount of zero causes RA to receive EXTS((RS)32:63), and CA and CA32 to be set to 0.

Operation

if 'srawi' then
    n ← SH
    r ← ROTL32((RS)32:63, 64-n)
    m ← MASK(n+32, 63)
    s ← (RS)32
    RA ← r&m | (64s) & ¬m
    carry ← s & ((r & ¬m)32:63 ≠ 0 )
    CA   ← carry
    CA32 ← carry

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.