vsubuhm

Vector Subtract Unsigned Halfword Modulo

vsubuhm vD, vA, vB

Subtracts 8 halfwords modulo 65536.

Details

The Vector Subtract Unsigned Halfword Modulo instruction subtracts each unsigned halfword element of VRB from the corresponding element in VRA, modulo 65536. The result is stored in VRT.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 7
   src1 ←EXTZ(VSR[VRA+32].hword[i])
   src2 ←EXTZ(VSR[VRB+32].hword[i])
   VSR[VRT+32].byte[i] ←CHOP8

Programming Note

This instruction is useful for performing element-wise subtraction of unsigned halfwords with modulo 65536, which can be particularly handy in graphics or audio processing where overflow needs to wrap around. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR register is set to enable vector operations. Be cautious of potential performance overhead if used in tight loops without optimization.

Example

vsubuhm vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1088
21
 
Format VX-form
Opcode 0x10000440
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B