vsubuhm

Vector Subtract Unsigned Halfword Modulo

vsubuhm vD, vA, vB

Subtracts 8 halfwords modulo 65536.

Details

Subtracts each of eight unsigned 16-bit halfwords in vB from the corresponding halfword in vA, with results modulo 2^16 (wrapping on underflow). No status flags are affected; this is a basic VMX/AltiVec arithmetic operation.

Pseudocode Operation

for i in 0 to 7 do
  vD[i*16:(i+1)*16-1] ← (vA[i*16:(i+1)*16-1] - vB[i*16:(i+1)*16-1]) mod 2^16

Programming Note

This instruction is useful for performing element-wise subtraction of unsigned halfwords with modulo 65536, which can be particularly handy in graphics or audio processing where overflow needs to wrap around. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR register is set to enable vector operations. Be cautious of potential performance overhead if used in tight loops without optimization.

Example

vsubuhm vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1088
21
 
Format VX-form
Opcode 0x10000440
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B