xsmulqp

VSX Scalar Multiply Quad-Precision

xsmulqp vD, vA, vB

Multiplies two quad-precision floating-point numbers and rounds the result to odd.

Encoding

Binary Layout

63

0:5

FRT

6:10

FRA

11:15

FRB

16:20

36

21:30

Rc

31

 

Format X-form

Opcode 0xFC000048

Extension VSX

Operands

• vD
  Target
• vA
  Source A
• vB
  Source B
• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

xsmulqp v2, v3, v4

// Scientific Quad-Float Multiply.

Registers Altered

vximz_flag, vxsnan_flag

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies two 128-bit quad-precision floating-point numbers held in VSX register pairs and stores the result in another VSX register pair, rounding to odd. The operation computes the full product and rounds using the round-to-odd mode to ensure correct rounding behavior. This instruction requires VSX support and updates FPSCR with exception flags.

Operation

FPR[vD:vD+1] ← quad_precision_round_to_odd(FPR[vA:vA+1] × FPR[vB:vB+1])
FPSCR ← updated with exception flags

Programming Note

The xsmulqp instruction handles special cases like NaNs and infinities, setting flags accordingly. Ensure proper handling of these conditions to avoid unexpected results. The instruction operates at the VSX privilege level and may raise exceptions for invalid operations. Performance can vary based on input values and rounding modes.