xsmulqp

VSX Scalar Multiply Quad-Precision

xsmulqp vD, vA, vB

Multiplies two quad-precision floating-point numbers and rounds the result to odd.

Details

The xsmulqp instruction multiplies two quad-precision floating-point numbers and rounds the result according to the specified rounding mode. If RO=0, the rounding mode is determined by FPSCR.RN; if RO=1, the rounding mode is Round to Odd.

Pseudocode Operation

if src1 is QNaN or SNaN then
    v <- src1
    vxsnan_flag <- 1
else if src2 is QNaN or SNaN then
    v <- src2
    vxsnan_flag <- 1
else if src1 is +Infinity and src2 is +Zero then
    v <- +Infinity
    vximz_flag <- 1
else if src1 is +Infinity and src2 is -Zero then
    v <- -Infinity
    vximz_flag <- 1
else if src1 is -Infinity and src2 is +Zero then
    v <- -Infinity
    vximz_flag <- 1
else if src1 is -Infinity and src2 is -Zero then
    v <- +Infinity
    vximz_flag <- 1
else if src1 is +Zero and src2 is +Infinity then
    v <- +Infinity
    vximz_flag <- 1
else if src1 is +Zero and src2 is -Infinity then
    v <- -Infinity
    vximz_flag <- 1
else if src1 is -Zero and src2 is +Infinity then
    v <- -Infinity
    vximz_flag <- 1
else if src1 is -Zero and src2 is -Infinity then
    v <- +Infinity
    vximz_flag <- 1
else
    v <- mul(src1, src2)
end if

Programming Note

The xsmulqp instruction handles special cases like NaNs and infinities, setting flags accordingly. Ensure proper handling of these conditions to avoid unexpected results. The instruction operates at the VSX privilege level and may raise exceptions for invalid operations. Performance can vary based on input values and rounding modes.

Example

xsmulqp v2, v3, v4

Encoding

Binary Layout
63
0
FRT
6
FRA
11
FRB
16
36
21
Rc
31
 
Format X-form
Opcode 0xFC000048
Extension VSX
Registers Altered vximz_flag, vxsnan_flag

Operands

  • vD
    Target
  • vA
    Source A
  • vB
    Source B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register