xscmpudp

VSX Scalar Compare Unordered Double-Precision

xscmpudp BF, XA, XB

Compares two double-precision floating-point values and sets the condition register based on the comparison.

Encoding

Binary Layout

111100

000000

Format XX3-form

Opcode 0xF0000118

Extension VSX

Operands

BF
CR Field
XA
Src A
XB
Src B
VS32
Target Vector Register

Example

xscmpudp cr0, vs2, vs3

Registers Altered

CR, FPSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction compares the double-precision floating-point value in doubleword element 0 of VSR[XA] with the double-precision floating-point value in doubleword element 0 of VSR[XB]. The result is placed into CR field BF and the FPCC. If either operand is a NaN, VXSNAN is set.

Operation

if 'xscmpudp' then
    src1 <- VSR[XA][0]
    src2 <- VSR[XB][0]
    cc <- C(src1, src2)
    FPCC <- cc
    CR[BF] <- cc
    if vxsnan_flag then
        fx(VXSNAN)
        if VE and not ignore-exception mode then
            error()

Programming Note

This instruction can be used to operate on single-precision source operands. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register.