xsrdpiz

VSX Scalar Round to Double-Precision Integer

xsrdpiz XT,XB

Rounds a double-precision floating-point value toward zero and places the result into a vector-scalar register.

Details

The instruction rounds the contents of doubleword element 0 of VSR[XB] toward zero and stores the result in doubleword element 0 of VSR[XT]. Doubleword element 1 of VSR[XT] is set to 0. The FPRF, FR, and FI fields are updated accordingly.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[XB+32].dword[0])
rnd ← bfp_ROUND_TO_INTEGER(0b001, src)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
vex_flag ← FPSCR.VE & vxsnan_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ← result
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
end
FPSCR.FR ← 0b0
FPSCR.FI ← 0b0

Programming Note

['This instruction can be used to operate on a single-precision source operand.', 'Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.']

Example

xsrdpiz vs1, vs3

Encoding

Binary Layout
18
0
T
6
B
11
BX
16
TX
21
 
Format XX2-form
Opcode 0xF0000164
Extension VSX
Registers Altered FPSCR (FPRF, FX, VXSNAN, FR, FI)

Operands

  • XT
    Target Vector-Scalar Register
  • XB
    Source Vector-Scalar Register