xssubqp

VSX Scalar Subtract Quad-Precision

xssubqp VRT,VRA,VRB
xssubqpo VRT,VRA,VRB

Subtracts the contents of two quad-precision floating-point registers and handles special cases like NaNs.

Details

The xssubqp instruction subtracts the value in VSR[VRB+32] from the value in VSR[VRA+32]. It handles various special cases such as NaNs, infinities, and zero differences.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ← bfp_CONVERT_FROM_BFP128(VSR[VRA+32])
src2 ← bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
v ← bfp_ADD(src1, bfp_NEGATE(src2))
rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
result ← bfp128_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vxisi_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then
do
    VSR[VRT+32] ← result
    FPSCR.FPRF ← fprf_CLASS_BFP128(result)
end
FPSCR.FR ← (vx_flag=0) & inc_flag
FPSCR.FI ← (vx_flag=0) & xx_flag

Programming Note

The xssubqp instruction is used for subtracting quad-precision floating-point numbers. Ensure that the VSX feature is enabled in the MSR register to avoid exceptions. Handle special cases like NaNs and infinities by checking the FPSCR flags after execution. The result is rounded according to the rounding mode specified in FPSCR.RN.

Example

xssubqp v1, v2, v3

Encoding

Binary Layout
63
0
FRT
6
FRA
11
FRB
16
514
21
Rc
31
 
Format X-form
Opcode 0xFC000404
Extension VSX
Registers Altered FPSCR FPRF FR FI FX VXSNAN VXISI OX UX XX

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector-Scalar Register
  • VRA
    Source Vector-Scalar Register
  • VRB
    Source Vector-Scalar Register