slbiag

SLB Invalidate All Global

slbiag RS,L

Invalidates all SLBs for a specified LPID and PID.

Encoding

Binary Layout

0

0:5

RS

6:10

L

11:14

0

15:31

 

Format X-form

Opcode 0x7C0006A4

Extension Base

Operands

• RS
  Source General Purpose Register
• L
  Logical flag (0 or 1)

Example

slbiag r3, 0

Registers Altered

LPIDR

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction invalidates all SLB entries for the target LPID and PID. If L=0, the target PID is taken from RS0:31. If executed in hypervisor state, the target LPID is taken from RS32:63; otherwise, it is taken from LPIDR.

Operation

if 'slbiag' then
    if L=0 then target_PID = RS0:31
    if MSRHV=1 then target_LPID = RS32:63
    else target_LPID = LPIDR
    for each nest SLB
        for each SLBE with LPID=target_LPID and (PID=target_PID | L=1)
            SLBEV ←0
            all other fields of SLBE ←undefined

Extended Mnemonics

Extended Mnemonic	Equivalent Instruction

Programming Note

slbiag does not affect SLBs on processor threads. slbiag serves as both a basic and an extended mnemonic. The Assembler will recognize an slbiag mnemonic with two operands as the basic form, and an slbiag mnemonic with one operand as the extended form. In the extended form the L operand is omitted and assumed to be 0.