icbtls

Instruction Cache Block Touch and Lock Set

icbtls CT, RA, RB

Locks an instruction cache line.

Details

Locks an instruction cache line in the L1 instruction cache at the address computed from RA+RB. The cache target (CT) field specifies the cache level and operation type. This is a privileged instruction that provides instruction cache locking hints and does not modify any general-purpose registers or condition flags.

Pseudocode Operation

EA ← (RA|0) + RB
Lock cache line at EA in L1 instruction cache based on CT

Example

icbtls 0, r4, r5

Encoding

Binary Layout
31
0
CT
6
RA
11
RB
16
486
21
/
31
 
Format X-form
Opcode 0x7C0003CC
Extension Privileged

Operands

  • CT
    Target
  • RA
    Base
  • RB
    Index