xxpermx

VSX Vector Permute Extended

xxpermx XT, XA, XB, XC, UIM

Permutes bytes from two source vectors using a control vector and a 3-bit selector.

Encoding

Binary Layout

1

0:5

8

6:8

0

9

/

10:31

60

32:37

XT

38:42

XA

43:47

XB

48:52

XC

53:57

UIM

58:63

 

Format XX4-form

Opcode 0x0500000088000000

Extension VSX

Operands

• XT
  Target
• XA
  Src A
• XB
  Src B
• XC
  Control
• UIM
  Selector
• VX1
  Target Vector Register
• VX2
  Source Vector Register
• VX3
  Source Vector Register

Example

xxpermx vs1, vs2, vs3, vs4, uim

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Permutes bytes from source vectors XA and XB using byte indices in XC, with a 3-bit UIM field selecting between different permutation modes. The permutation control bytes in XC determine which source byte maps to each position in XT. This VSX instruction does not affect condition registers or status fields.

Operation

for i in 0 to 15:
  idx ← (XC[8*i:8*i+7] & 0x1F) | (UIM << 5)
  if idx < 16:
    XT[8*i:8*i+7] ← XA[8*idx:8*idx+7]
  else:
    XT[8*i:8*i+7] ← XB[8*(idx-16):8*(idx-16)+7]

Programming Note

The following is an example of emulating 256-bit xxperm, where a 256-bit vector is contained in a pair of VSRs. The instruction is capable of emulating up to a 2048-bit xxperm.