xststdcsp

VSX Scalar Test Data Class Single-Precision

xststdcsp BF, vB, DCM

Tests the data class of a single-precision floating-point value in a VSX register and sets condition bits accordingly.

Encoding

Binary Layout

DCM

298

Format XX2-form

Opcode 0xF00004A8

Extension VSX

Operands

BF
CR Field
vB
Source
DCM
Mask
XB
Index of VSX register containing the double-precision floating-point value
DCMX
Data Class Mask

Example

xststdcsp cr0, vb, 0

Registers Altered

CR, FPSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction tests the data class of the double-precision floating-point value in the doubleword element 0 of VSR[XB] and sets the corresponding condition bits in CR field BF and FPCC based on the specified data classes in DCMX.

Operation

if MSR.VSX=0 then
    VSX_Unavailable()
src ← VSR[32×BX+B].dword[0]
exponent ← src.bit[1:11]
fraction ← src.bit[12:63]
class.Infinity ← (exponent = 0x7FF) & (fraction = 0)
class.NaN ← (exponent = 0x7FF) & (fraction != 0)
class.Zero ← (exponent = 0x000) & (fraction = 0)
class.Denormal ← (exponent = 0x000) & (fraction != 0) | (exponent > 0x000) & (exponent < 0x381)
match ← (DCMX.bit[0] & class.NaN) | (DCMX.bit[1] & class.Infinity & !sign) | (DCMX.bit[2] & class.Infinity & sign) | (DCMX.bit[3] & class.Zero & !sign) | (DCMX.bit[4] & class.Zero & sign) | (DCMX.bit[5] & class.Denormal & !sign) | (DCMX.bit[6] & class.Denormal & sign)
not_SP_value ← ¬bfp64_IS_BFP32_VALUE(src)
CR.bit[4×BF] ← FPSCR.FL ← src.sign
CR.bit[4×BF+1] ← FPSCR.FG ← 0b0
CR.bit[4×BF+2] ← FPSCR.FE ← match
CR.bit[4×BF+3] ← FPSCR.FU ← not_SP_value

Programming Note

This instruction is used to test the data class of a single-precision floating-point value in VSX registers. Ensure that the VSX facility is enabled (MSR.VSX=1) before using this instruction, otherwise it will raise an exception. The result sets condition bits in CR and FPSCR, which can be used for conditional branching based on the tested data class. Be cautious with alignment; the source value must be properly aligned within the VSR register to avoid undefined behavior.