xsrdpip

VSX Scalar Round to Double-Precision Integer using round toward +Infinity

xsrdpip XT,XB

Rounds a double-precision floating-point value towards positive infinity and stores the result in a vector scalar register.

Encoding

Binary Layout

0:5

6:10

105

11:15

16:20

21:31

Format XX2-form

Opcode 0xF00001A4

Extension VSX

Operands

XT
Target Vector Scalar Register
XB
Source Vector Scalar Register

Example

xsrdpip vs1, vs3

Registers Altered

FPSCR, FPRF, VXSNAN, FR, FI

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction rounds the contents of doubleword element 0 of VSR[XB] towards positive infinity. The result is placed into doubleword element 0 of VSR[XT], with doubleword element 1 set to zero. FPRF is updated based on the class and sign of the result, while FR and FI are reset to zero.

Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[VRB+32].dword[0])
rnd ← bfp_ROUND_TO_INTEGER(0b010, src)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
vex_flag ← FPSCR.VE & vxsnan_flag
if vex_flag=0 then
do
    VSR[32×TX+T].dword[0] ← result
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
end
FPSCR.FR ← 0b0
FPSCR.FI ← 0b0

Programming Note

This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.