xsmsubqpo

VSX Scalar Multiply-Subtract Quad-Precision (Overflow)

xsmsubqpo VRT,VRA,VRB

Performs a multiply-subtract operation on quad-precision floating-point values.

Encoding

Binary Layout

18

0:5

VRT

6:10

VRA

11:15

VRB

16:20

RO

21:31

 

Format X-form

Opcode 0xFC000348

Extension VSX

Operands

• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

xsmsubqp v1, v2, v3

Registers Altered

FPSCR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a scalar multiply-subtract operation on quad-precision floating-point values, computing VRT = VRT - (VRA × VRB). The result is rounded according to the current rounding mode in FPSCR. This instruction requires VSX support and updates FPSCR exception flags based on the operation result.

Operation

VRT[0:127] ← VRT[0:127] - (VRA[0:127] × VRB[0:127])
FPSCR ← update_exception_flags(FPSCR, result)

Programming Note

The xsmsubqp instruction is used for performing a multiply-subtract operation on quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid an exception. Be cautious of rounding modes and exceptions, as they can affect the result and set flags in the FPSCR register. This instruction operates on 128-bit aligned data in vector registers VSR[VRA+32], VSR[VRT+32], and VSR[VRB+32].