xsrqpi

VSX Scalar Round Quad-Precision to Integer

xsrqpi vD, vB, R

Rounds a quad-precision floating-point value in VRB to an integer and places the result in VRT.

Encoding

Binary Layout

63

0:5

VRT

6:10

///

11:14

R

15

VRB

16:20

RMC

21:22

5

23:30

EX

31

 

Format Z23-form

Opcode 0xFC00000A

Extension VSX

Operands

• vD
  Target
• vB
  Source
• R
  Mode
• VRT
  Target Vector Register
• VRB
  Source Vector Register
• RMC
  Rounding Mode Control

Example

xsrqpi vd, vb, 0

Registers Altered

FPSCR, VXSNAN, FX

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Rounds a 128-bit quad-precision floating-point value in VSR vB to an integer value using rounding mode R, placing the result back in VSR vD as a quad-precision value. The rounding mode R is encoded in bit 31 (0=round-to-nearest-even, 1=round-toward-zero). FPSCR exception flags (XX, ZX) are updated based on the rounding operation. Requires VSX support.

Operation

rmode ← (R == 0) ? RoundToNearestEven : RoundTowardZero
vD ← RoundToInteger(vB, rmode) as quad-precision
FPSCR[XX,ZX] ← updated based on rounding result

Programming Note

The xsrqpi instruction is used to round a quad-precision floating-point value to an integer. Ensure that the VSX feature is enabled in the MSR register. Be cautious with NaN values, as they can trigger exceptions and set specific flags. The rounding mode is determined by the RMC field and the FPSCR.RN setting when R=0.