xsxsigdp

VSX Scalar Extract Significand Double-Precision

xsxsigdp XT, XB

Extracts the significand of a double-precision floating-point value from a VSX register and places it into a general-purpose register.

Encoding

Binary Layout

60

0:5

XT

6:10

/

11:15

XB

16:20

347

21:29

BX

30

TX

31

 

Format XX2-form

Opcode 0xF001056C

Extension VSX

Operands

• XT
  Target
• XB
  Source
• RT
  Target General Purpose Register
• VS32
  Target Vector Register
• VS31
  Source Vector Register

Example

xsxsigdp vs1, vs3

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Extracts the significand (mantissa) from a double-precision floating-point value in XB and places it as a 52-bit value into the lower half of XT, sign-extended. This instruction isolates the fractional part of the floating-point representation. Requires VSX support.

Operation

XT ← (0x0000000000000000 || significand(XB[32:63]))

Programming Note

This instruction can be used to operate on a single-precision source operand.