xvnmaddasp

Vector Negative Multiply-Add Single-Precision Type-A

xvnmaddasp XT,XA,XB

Performs a negative multiply-add operation on single-precision floating-point elements.

Encoding

Binary Layout

60

0:5

XT

6:10

XA

11:15

XB

16:20

1544

21:31

 

Format XX3-form

Opcode 0xF0000608

Extension VSX

Operands

• XT
  Target Vector Register
• XA
  Source Vector Register
• XB
  Source Vector Register

Example

xvnmaddasp vs1, vs2, vs3

Registers Altered

FPSCR, VXSNAN, VXIMZ, Vxisi, OX, UX, XX

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a negative multiply-add operation on single-precision floating-point vector elements (XT ← -(XA × XB) + XT) using Type-A fused arithmetic. This VSX instruction operates on 128-bit vector registers each containing four single-precision values. The operation does not affect condition registers; rounding and exception behavior follows FPSCR settings.

Operation

XT ← -(XA × XB) + XT

Programming Note

This instruction is commonly used in vectorized floating-point computations where negative multiplication and addition are required. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking MSR.VSX before using this instruction. Be aware of potential exceptions such as NaNs, infinities, or underflows, which can set flags in FPSCR and may trigger exceptions based on the current settings.