xvnmaddasp

Vector Negative Multiply-Add Single-Precision Type-A

xvnmaddasp XT,XA,XB

Performs a negative multiply-add operation on single-precision floating-point elements.

Details

Performs a negative multiply-add operation on single-precision floating-point vector elements (XT ← −(XA × XB) + XT) using Type-A fused arithmetic. This VSX instruction operates on 128-bit vector registers each containing four single-precision values. The operation does not affect condition registers; rounding and exception behavior follows FPSCR settings.

Pseudocode Operation

XT ← −(XA × XB) + XT

Programming Note

This instruction is commonly used in vectorized floating-point computations where negative multiplication and addition are required. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking MSR.VSX before using this instruction. Be aware of potential exceptions such as NaNs, infinities, or underflows, which can set flags in FPSCR and may trigger exceptions based on the current settings.

Example

xvnmaddasp vs1, vs2, vs3

Encoding

Binary Layout
60
0
XT
6
XA
11
XB
16
1544
21
 
Format XX3-form
Opcode 0xF0000608
Extension VSX
Registers Altered FPSCR, VXSNAN, VXIMZ, Vxisi, OX, UX, XX

Operands

  • XT
    Target Vector Register
  • XA
    Source Vector Register
  • XB
    Source Vector Register