stvehx

Store Vector Element Halfword Indexed X-form

stvehx VRS,RA,RB

Stores a halfword element from a vector register to memory.

Details

The stvehx instruction stores a halfword element from the vector register VRS+32 into memory at an address calculated from registers RA and RB.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
EA ←EA & 0xFFFF_FFFF_FFFF_FFFE
eb ←EA.bit[60:63]
if Big-Endian byte ordering then
    MEM(EA,2) ←VSR[VRS+32].byte[eb:eb+1]
else
    MEM(EA,2) ←VSR[VRS+32][14-eb:15-eb]

Programming Note

Unless bits 60:62 of the address are known to match the halfword offset of the subject halfword element in VSR[VRS+32], software should use Vector Splat to splat the subject halfword element before performing the store.

Example

stvehx v1, r4, r5

Encoding

Binary Layout
011111
0
VRS
6
RA
11
RB
16
00101
21
00111
26
Rc
31
 
Format X-form
Opcode 0x7C00014E
Extension VMX (AltiVec)

Operands

  • VRS
    Vector Register
  • RA
    Source General Purpose Register
  • RB
    Source General Purpose Register