vsro

Vector Shift Right by Octet

vsro vD, vA, vB

Shifts vector right by byte count.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

1100

21:31

 

Format VX-form

Opcode 0x1000044C

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Data
• vB
  Shift Count

Example

vsro vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Shifts the 128-bit value in vA right by the number of octets (bytes) specified in the low 4 bits of vB, filling vacated positions on the left with zeros. This instruction is similar to vsr but uses only the low 4 bits of the shift count, limiting the shift to 0-15 bytes. No condition register fields are affected.

Operation

shift_count ← vB[124:127]
vD ← vA >> (shift_count * 8)

Programming Note

The vsro instruction shifts the contents of a vector register right by a specified number of bytes. Ensure that the shift amount is within the valid range (0-15) to avoid undefined behavior. This instruction requires the VEC bit in the MSR to be set; otherwise, it will raise an exception. Be cautious with alignment as shifting by byte boundaries can lead to unexpected results if not handled properly.