vsrq

Vector Shift Right Quadword

vsrq vD, vA, vB

Shifts the contents of a vector register right by a specified number of bits.

Details

Shifts the 128-bit contents of the source vector right by the number of bits specified in the shift-count register and stores the result in the destination vector. Bits shifted out the right end are discarded; zeros are shifted in from the left. The shift amount is taken modulo 128. No condition flags are affected; this is a VMX/AltiVec instruction.

Pseudocode Operation

shiftAmount ← vB[121:127] mod 128
vD[0:127] ← vA[0:127] >> shiftAmount
vD[0:(127-shiftAmount)] ← 0 (shifted-in zeros)

Programming Note

The vsrq instruction requires the Vector Facility to be enabled in the MSR register. Ensure that the shift amount is within the range of 0-127 bits to avoid unexpected results. The operation is performed on quadword elements, so alignment considerations are not necessary for this specific instruction.

Example

vsrq vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
517
 
Format VX-form
Opcode 0x10000205
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Data
  • vB
    Shift
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register