vspltisw

Vector Splat Immediate Signed Word

vspltisw vD, SIM

Splat a signed immediate value into all elements of a vector register.

Details

The vspltisw instruction splats an immediate signed word value across all elements of a vector register. It sign-extends the 16-bit SIM field to 32 bits and replicates this value in each of the four word elements of the target vector register.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 3
   VSR[VRT+32].word[i] ←EXTS32(SIM, 32)
end

Programming Note

The vspltisw instruction is commonly used to initialize a vector register with a repeated signed word value. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The immediate value is sign-extended from 16 bits to 32 bits and replicated across all four elements of the target vector register.

Example

vspltisw vd, 4

Encoding

Binary Layout
000100
0
vD
6
SIM
11
//
16
01110
21
001100
26
 
Format VX-form
Opcode 0x1000038C
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • SIM
    Immediate
  • VRT
    Target Vector Register
  • SI16
    Signed Immediate Value (16-bit)