vspltisw

Vector Splat Immediate Signed Word

vspltisw vD, SIM

Splat a signed immediate value into all elements of a vector register.

Encoding

Binary Layout

000100

0:5

vD

6:10

SIM

11:15

//

16:20

01110

21:25

001100

26:31

 

Format VX-form

Opcode 0x1000038C

Extension VMX (AltiVec)

Operands

• vD
  Target
• SIM
  Immediate
• VRT
  Target Vector Register
• SI16
  Signed Immediate Value (16-bit)

Example

vspltisw vd, 4

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Splats a 5-bit signed immediate value into all 4 word elements of vD, sign-extended to 32 bits per word. The immediate SIM is a signed 5-bit value (range -16 to 15). No status flags are affected. This is a VMX/AltiVec instruction.

Operation

value ← sign_extend(SIM, 32)
vD ← replicate(value to all 4 word positions)

Programming Note

The vspltisw instruction is commonly used to initialize a vector register with a repeated signed word value. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The immediate value is sign-extended from 16 bits to 32 bits and replicated across all four elements of the target vector register.