Instruction Cache Synchronisation
Make newly written instructions visible to the fetch unit.
Memory System
Semantics
The problem every JIT and every self-modifying program has: code has just been stored as data, and the processor must be made to fetch it rather than a stale copy. Whether anything is required at all is the sharpest split among these four.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | none | not available | Nothing is required. x86 keeps instruction and data caches coherent in hardware, so code can be written and jumped to with no maintenance at all. A serialising instruction is sometimes used to discard already-prefetched bytes, but no cache is ever invalidated. This is a real cost in hardware that the other three decline to pay. |
| ARM | an idiom | Three steps, in order: clean the data cache to the point of unification, IC IVAU to invalidate the instruction cache line, then ISB so the core refetches. Omitting the ISB is a classic JIT bug that appears only on some implementations, which is what makes it expensive to find. | |
| RISC-V | one instruction | A single FENCE.I orders instruction fetch against that hart's earlier stores. It is only local: making code visible to another hart needs an inter-processor interrupt, and the base ISA provides no instruction for that. | |
| PowerISA | an idiom | DCBST pushes the line out of the data cache, ICBI invalidates the instruction cache, and ISYNC forces a refetch. The same three-step shape as ARM's. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call