Return From Exception

Resume the interrupted program after handling a trap or interrupt.

System

Semantics

Restore the saved program counter and processor state atomically, so that the return cannot be observed half-done. Where that state was saved is what differs.

Architecture Instructions Expressed as How this architecture does it
x86 one instruction IRET pops CS:RIP and RFLAGS from the stack, so the return path depends on the stack being intact. SYSRET is the faster return from SYSCALL and restores less state, a shortcut that has produced several privilege-escalation errata.
ARM one instruction ERET restores PC from ELR_ELn and PSTATE from SPSR_ELn, dedicated registers rather than memory, so the return touches no stack and cannot fault.
RISC-V one instruction One instruction per privilege level, taking the address from that level's own EPC CSR. The mechanism is identical at each level, which is the same uniformity that shows up throughout the privileged spec.
PowerISA one instruction RFID restores from SRR0 and SRR1, the save and restore registers the hardware writes when the interrupt is taken.

Other operations

Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call