Cache Line Flush
Write back and/or invalidate a cache line by address.
Memory System
Semantics
Forces a cache line to memory, invalidates it, or both. Central to persistent-memory programming and to several cache-timing side-channel mitigations.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | CLFLUSH invalidates and writes back a line; CLFLUSHOPT is the weakly ordered version, and CLWB writes back while keeping the line cached. | |
| ARM | one instruction | A single DC instruction whose operand names the operation, such as DC CVAC (clean by virtual address to point of coherency) or DC CIVAC (clean and invalidate). | |
| RISC-V | one instruction | Zicbom cache-block management: separate CBO.CLEAN, CBO.FLUSH, and CBO.INVAL instructions. | |
| PowerISA | one instruction | dcbf flushes a data cache block; dcbst stores without invalidating, and icbi handles the instruction cache. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call