CPU Feature Detection
Ask the processor at runtime which instructions and extensions it actually implements.
System
Semantics
Software compiled once must run on many implementations of the same architecture. The question is whether the answer comes from an unprivileged instruction, a privileged register the OS has to relay, or a table looked up by model number.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | A single unprivileged instruction. CPUID returns feature bits in EAX/EBX/ECX/EDX for the leaf selected in EAX, so user code can dispatch on features with no help from the operating system. This is why runtime CPU dispatch is routine on x86 and awkward elsewhere. | |
| ARM | one instruction | The ID_AA64ISAR* and ID_AA64PFR* registers describe the implementation and are read with MRS, but they are EL1-only. User code on Linux reads the kernel's HWCAP auxiliary vector instead, so discovery is architectural while access to it is not. | |
| RISC-V | an idiom | The misa CSR reports the base width and the single-letter extensions, read via CSRR, and CSRs are privileged. Multi-letter extensions such as Zbb do not appear in misa at all, so real discovery goes through the device tree or the riscv_hwprobe syscall rather than any instruction. | |
| PowerISA | one instruction | MFPVR, a specialised MFSPR, returns the Processor Version Register identifying the implementation. Capabilities are then looked up per model rather than queried bit by bit, and Linux exposes the result through AT_HWCAP. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Memory Barrier / Fence No Operation Population Count Read Cycle Counter Rotate Left Sign Extend Byte Spin-Wait Hint System Call