cpuid

CPU Identification

CPUID

Returns processor information based on EAX value.

Details

Executes CPU identification, returning processor feature information and capabilities into EAX, EBX, ECX, and EDX based on the input value in EAX (and sometimes ECX). This is a privileged instruction in some contexts and causes a serializing event; it clears the pipeline and blocks out-of-order execution until completion. The exact output depends on the EAX input leaf and subleaf (ECX) values.

Pseudocode Operation

EAX, EBX, ECX, EDX ← cpuid_data[EAX, ECX];

Example

CPUID

Encoding

Binary Layout
0F
+0
A2
+1
 
Format Legacy
Opcode 0F A2
Extension Base

Operands

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
0F A2 CPUID ZO Valid Valid Returns processor identification and feature information to the EAX, EBX, ECX, and EDX registers, as determined by input entered in EAX and, in some cases, ECX.

Description

The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can set and clear this flag, the processor executing the procedure supports the CPUID instruction. This instruction operates the same in non-64-bit modes and 64-bit mode. CPUID returns processor identification and feature information in the EAX, EBX, ECX, and EDX registers.1 The instruction’s output is dependent on the contents of the EAX register upon execution and, in some cases, ECX. Chapter 21, “Processor Identification and Feature Determination,” in Volume 1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual provides CPUID leaf information and shows information returned, depending on the initial value loaded into the EAX and ECX registers. CPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution guarantees that any modifications to flags, registers, and memory for previous instructions are completed before the next instruction is fetched and executed. Although the CPUID instruction provides serialization, it is not the preferred method on newer processors that support the SERIALIZE instruction. See “Serializing Instructions” in Chapter 11 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A for more details. Execution of CPUID causes a VM exit when executed in VMX non-root operation. See Chapter 27, “Virtual Machine Control Structures,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C for more details. IA-32 Architecture Compatibility CPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the Intel486 processor.

Operation

IA32_BIOS_SIGN_ID MSR := Update with installed microcode revision number;
(* Note that for some leaf values in EAX, the subleaf value in ECX is ignored. *)
(* Note that for invalid CPUID leaves and subleaves, the output values returned in EAX, EBX, ECX, and EDX are “Reserved” *)
(* Refer to Volume 1, Chapter 21 for details surrounding CPUID_INFO() *)
(EAX, EBX, ECX, EDX) := CPUID_INFO(EAX, ECX)

Flags Affected

None. Exceptions (All Operating Modes) #UD If the LOCK prefix is used. 1. On Intel 64 processors, CPUID clears the high 32 bits of the RAX/RBX/RCX/RDX registers in all modes. CPUID—CPU Identification Vol. 2A 3-203 In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruction results in an invalid opcode (#UD) exception being generated. CPUID—CPU Identification Vol. 2A 3-204