bextr

Bit Field Extract

BEXTR r32, r/m32, r32

Extracts sequence of bits from source using index/length.

Details

Extracts a contiguous sequence of bits from src1 specified by the start position and length encoded in src2 (bits 7:0 = start, bits 15:8 = length), storing the extracted bits in dest. ZF is set if the result is zero; CF and OF are cleared; AF and PF are undefined. Available in 32-bit and 64-bit sizes; requires BMI1 extension.

Pseudocode Operation

start ← src2[0:7]
length ← src2[8:15]
if length == 0:
  dest ← 0
else if (start + length) > 32:
  dest ← 0
else:
  dest ← (src1 >> start) & ((1 << length) - 1)
ZF ← (dest == 0)
CF ← 0
OF ← 0
AF ← undefined
PF ← undefined

Example

BEXTR eax, ebx, eax

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format VEX
Opcode VEX.LZ.0F38.W0 F7 /r
Extension BMI1

Operands

  • dest
    32-bit general-purpose register (e.g. EAX)
  • src1
    32-bit register or memory
  • src2
    32-bit general-purpose register (e.g. EAX)

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.LZ.0F38.W0 F7 /r BEXTR r32a, r/m32, r32b RMV V/V BMI1 Contiguous bitwise extract from r/m32 using r32b as control; store result in r32a.
VEX.LZ.0F38.W1 F7 /r BEXTR r64a, r/m64, r64b RMV V/N.E. BMI1 Contiguous bitwise extract from r/m64 using r64b as control; store result in r64a.

Description

Extracts contiguous bits from the first source operand (the second operand) using an index value and length value specified in the second source operand (the third operand). Bit 7:0 of the second source operand specifies the starting bit position of bit extraction. A START value exceeding the operand size will not extract any bits from the second source operand. Bit 15:8 of the second source operand specifies the maximum number of bits (LENGTH) beginning at the START position to extract. Only bit positions up to (OperandSize -1) of the first source operand are extracted. The extracted bits are written to the destination register, starting from the least significant bit. All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed. The destination register is cleared if no bits are extracted. This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

START := SRC2[7:0];
LEN := SRC2[15:8];
TEMP := ZERO_EXTEND_TO_512 (SRC1 );
DEST := ZERO_EXTEND(TEMP[START+LEN -1: START]);
ZF := (DEST = 0);

Intel C/C++ Compiler Intrinsic Equivalent

BEXTR unsigned __int32 _bextr_u32(unsigned __int32 src, unsigned __int32 start. unsigned __int32 len);
BEXTR unsigned __int64 _bextr_u64(unsigned __int64 src, unsigned __int32 start. unsigned __int32 len);

Flags Affected

ZF is updated based on the result. AF, SF, and PF are undefined. All other flags are cleared.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-29, “Type 13 Class Exception Conditions,” additionally: #UD If VEX.W = 1. BEXTR—Bit Field Extract Vol. 2A 3-77