lahf

Load Flags into AH

LAHF

Loads bits 0, 2, 4, 6, and 7 of EFLAGS into AH.

Details

Loads the lower byte of EFLAGS into the AH register, extracting flags CF, PF, AF, ZF, and SF. Bits 1, 3, and 5 are set to 0, bit 7 contains SF, and bits 0, 2, 4, 6 contain CF, PF, AF, ZF respectively. This is commonly used to save flag state for later restoration with SAHF.

Pseudocode Operation

AH ← 0; AH[0] ← CF; AH[2] ← PF; AH[4] ← AF; AH[6] ← ZF; AH[7] ← SF;

Example

LAHF

Encoding

Binary Layout

Format Legacy

Opcode 9F

Extension Base

Operands

Reference (Intel® SDM)

Instruction Forms

Opcode	Instruction	Op/En	64/32-bit Mode	CPUID	Description
9F	LAHF	ZO	Invalid1 Valid		Load: AH := EFLAGS(SF:ZF:0:AF:0:PF:1:CF).

Description

This instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF_SAHF_64[0] = 1.

Operation

IF 64-Bit ModeTHENIF CPUID.80000001H:ECX.LAHF_SAHF_64[0] = 1;THEN AH := RFLAGS(SF:ZF:0:AF:0:PF:1:CF);ELSE #UD; FI;ELSEAH
:= EFLAGS(SF:ZF:0:AF:0:PF:1:CF);FI;

Flags Affected

None. The state of the flags in the EFLAGS register is not affected.

Exceptions

Protected Mode Exceptions

#UD If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#UD If CPUID.80000001H:ECX.LAHF_SAHF_64[0] = 0. If the LOCK prefix is used. LAHF—Load Status Flags Into AH Register Vol. 2A 3-532