blsmsk

Get Mask Up to Lowest Set Bit

BLSMSK r32, r/m32

Creates mask up to lowest set bit (x ^ (x-1)).

Details

Creates a mask of all bits set from bit 0 up to and including the lowest set bit in src by computing (src ^ (src - 1)), storing the result in dest. ZF is set if src is zero; CF is set if src is zero; OF is cleared; AF and PF are undefined. Available in 32-bit and 64-bit sizes; requires BMI1 extension.

Pseudocode Operation

dest ← src ^ (src - 1)
ZF ← (src == 0)
CF ← (src == 0)
OF ← 0
AF ← undefined
PF ← undefined

Example

BLSMSK eax, ebx

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format VEX
Opcode VEX.LZ.0F38.W0 F3 /2
Extension BMI1

Operands

  • dest
    32-bit general-purpose register (e.g. EAX)
  • src
    32-bit register or memory

Reference (Intel® SDM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
VEX.LZ.0F38.W0 F3 /2 BLSMSK r32, r/m32 VM V/V BMI1 Set all lower bits in r32 to “1” starting from bit 0 to lowest set bit in r/m32.
VEX.LZ.0F38.W1 F3 /2 BLSMSK r64, r/m64 VM V/N.E. BMI1 Set all lower bits in r64 to “1” starting from bit 0 to lowest set bit in r/m64.

Description

Sets all the lower bits of the destination operand to “1” up to and including lowest set bit (=1) in the source operand. If source operand is zero, BLSMSK sets all bits of the destination operand to 1 and also sets CF to 1. This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

temp := (SRC-1) XOR (SRC) ;
SF := temp[OperandSize -1];
ZF := 0;
IF SRC = 0
CF := 1;
ELSE
CF := 0;
FI
DEST := temp;

Intel C/C++ Compiler Intrinsic Equivalent

BLSMSK unsigned __int32 _blsmsk_u32(unsigned __int32 src);
BLSMSK unsigned __int64 _blsmsk_u64(unsigned __int64 src);

Flags Affected

SF is updated based on the result. CF is set if the source if zero. ZF and OF flags are cleared. AF and PF flag are undefined.

Exceptions

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-29, “Type 13 Class Exception Conditions.” BLSMSK—Get Mask Up to Lowest Set Bit Vol. 2A 3-88