vprotb

Vector Packed Rotate Byte

VPROTB xmm1, xmm2/m128, imm8

Rotates bytes in XMM register.

Details

Rotates each byte within a 128-bit XMM register by the amount specified in the 8-bit signed immediate, with rotation direction determined by the sign of the immediate (positive = left rotate, negative = right rotate). This XOP instruction is part of the AMD Bulldozer-era vector extensions and does not modify CPU flags.

Pseudocode Operation

for i in 0..15:
  if (imm8 >= 0):
    xmm1[i*8+7:i*8] ← ROL(src1[i*8+7:i*8], imm8 & 7)
  else:
    xmm1[i*8+7:i*8] ← ROR(src1[i*8+7:i*8], (-imm8) & 7)

Example

VPROTB xmm1, xmm2/m128, 3

Encoding

Binary Layout
VEX
+0
opcode
+3
ModRM
+4
 
Format XOP
Opcode XOP.128.08.W0 C0 /r ib
Extension XOP

Operands

  • dest
    128-bit XMM SIMD register
  • src1
    128-bit XMM SIMD register or Memory operand
  • src2
    8-bit signed immediate

Reference (AMD APM)

Instruction Forms

Opcode Instruction Op/En 64/32-bit Mode CPUID Description
8F RXB.09 0.count.0.00 90 /r VPROTB xmm1, xmm2/mem128, xmm3
8F RXB.09 1.src.0.00 90 /r VPROTB xmm1, xmm2, xmm3/mem128
8F RXB.08 0.1111.0.00 C0 /r ib VPROTB xmm1, xmm2/mem128, imm8

Description

Bytes Rotates each byte of the source as specified by a count operand and writes the result to the corresponding byte of the destination. There are two versions of the instruction, one for each source of the count byte: • VPROTB dest, src, fixed-count • VPROTB dest, src, variable-count For both versions of the instruction, the destination (dest) operand is an XMM register specified by ModRM.reg. The fixed-count version of the instruction rotates each byte of the source (src) the number of bits specified by the immediate fixed-count byte. All bytes are rotated the same amount. The source XMM register or memory location is selected by the ModRM.r/m field. The variable-count version of the instruction rotates each byte of the source the amount specified in the corresponding byte element of the variable-count. Both src and variable-count are configured by XOP.W. • When XOP.W = 0, variable-count is an XMM register specified by XOP.vvvv and src is either an XMM register or a 128-bit memory location specified by ModRM.r/m. • When XOP.W = 1, variable-count is either an XMM register or a 128-bit memory location specified by ModRM.r/m and src is an XMM register specified by XOP.vvvv. When the count value is positive, bits are rotated to the left (toward the more significant bit positions). The bits rotated out left of the most significant bit are rotated back in at the right end (least-significant bit) of the byte. When the count value is negative, bits are rotated to the right (toward the least significant bit positions). The bits rotated to the right out of the least significant bit are rotated back in at the left end (most-significant bit) of the byte. Bits [255:128] of the YMM register that corresponds to the destination are cleared.

Flags Affected

None None

Exceptions

Exceptions

Mode Exception Cause of Exception Real Virt Prot X Instruction not supported, as indicated by CPUID feature identifier. X X XOP instructions are only recognized in protected mode. X CR4.OSXSAVE = 0, indicated by CPUID Fn0000_0001_ECX[OSXSAVE]. X XFEATURE_ENABLED_MASK[2:1] ! = 11b. Invalid opcode, #UD X XOP.vvvv ! = 1111b (for immediate operand variant only) X XOP.L field = 1. X REX, F2, F3, or 66 prefix preceding XOP prefix. X Lock prefix (F0h) preceding opcode. Device not available, #NM X CR0.TS = 1. Stack, #SS X Memory address exceeding stack segment limit or non-canonical. X Memory address exceeding data segment limit or non-canonical. General protection, #GP X Null data segment used to reference memory. Page fault, #PF X Instruction execution caused a page fault. Alignment check, #AC X Memory operand not 16-byte aligned when alignment checking enabled. X — XOP exception 822 [AMD VPROTBPublic Use] Instruction Reference